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Portfolio

Engineering

Five years of co-op and coursework across two domains that share a discipline: making hardware behave correctly under real-time constraints. Pick a track below.

Languages

  • C/C++
  • Python
  • SystemVerilog
  • Verilog/VHDL
  • MATLAB
  • Tcl

Tools

  • Xilinx Vivado
  • Synopsys Design Compiler
  • Cadence Innovus
  • Simulink/Stateflow
  • Altium Designer

Protocols

  • AXI4 / AXI-Stream
  • CAN / CAN FD
  • JTAG / I2C / SPI
  • PCIe / UART