Hardware & FPGA
Deep dive into RTL design, SystemVerilog, and Digital Signal Processing. Featuring Real-Time SDR and Image Acceleration projects.
Work Experience
Embedded Software/Electronics Engineer Coop @ Christie Digital Systems
May 2024 — Aug 2025- Architected a hardware-software co-design solution by integrating a MicroBlaze soft-core processor via AXI4-Lite interconnects to orchestrate control flow for a SystemVerilog video pipeline.
- Debugged complex FPGA designs using JTAG-based hardware debugging, Xilinx SDK for real-time register access, and Virtual I/O cores for in-system signal probing, significantly reducing hardware iteration time.
- Migrated and synthesized legacy RTL IP cores to the Xilinx UltraScale+ architecture, achieving timing closure at target frequencies and optimizing logic utilization for future-generation production boards.
- Designed, implemented, and verified RTL for a custom hardware block, independently creating a SystemVerilog testbench, using DVE waveform analysis for validation, and resolving functional bugs and lint errors to meet production standards.
- Engineered a self-checking SystemVerilog testbench for UART protocol verification, designing constrained-random test vectors to identify critical corner cases (parity/framing errors).
Research Assistant II @ McMaster University - Stellantis
May 2023 — Aug 2023- Designed and fabricated mounting hardware in Autodesk Inventor to integrate Hall effect current transducers into a 6-phase inverter setup, enabling non-invasive phase current measurement across HV lines.
- Executed incremental board bring-up of high-power DC motor control PCBs, validating HV rail connections from a safety box to the 6-phase inverter using oscilloscopes and multimeters.
- Developed MATLAB scripts to analyze time-series test data, extracting key metrics (mean, max, range) to evaluate inverter setup performance across varying operating parameters.
Key Projects
Multi-Cycle MIPS CPU
Designed a multi-cycle MIPS processor with an 8-state one-hot FSM, shared-adder ALU, and 32×32 register file. Optimized power via enable-gated pipeline registers and ALU input isolation, and timing via pre-computed branch targets and a balanced OR reduction tree. Synthesized on ASAP7 7nm with clock gating and verified through gate-level simulation with SDF back-annotated timing.
- Verilog
- Synopsys DC
- ASAP7 7nm
- NCVerilog
- GLS
Fixed-Point ALU with MAC & Overflow Detection
Implemented a signed fixed-point ALU (7-bit integer, 5-bit fraction) supporting 8 operations including addition, subtraction, multiplication, multiply-accumulate (MAC), XNOR, ReLU, mean, and absolute maximum. Designed persistent overflow assertion across uninterrupted MAC sequences and verified against constrained-random test vectors.
- Verilog
- NCVerilog
- DVE
- Fixed-Point
Real-Time Software Defined Radio (SDR) Receiver
Developed a multi-threaded C++ pipeline to demodulate real-time FM mono/stereo audio from raw 8-bit IQ samples, implementing FIR filters, block convolution, and fractional resampling. Implemented Radio Data System digital decoding path including carrier recovery via squaring nonlinearity, matched filtering, and Manchester decoding.
- C++
- DSP
- Linux
- Multithreading
Hardware-Accelerated Image Decompression System
Architected a SystemVerilog upsampling and colorspace conversion pipeline on an Altera DE2 FPGA, implementing a 6-tap FIR filter using shared MAC blocks with ≥75% multiplier utilization. Implemented fixed-point block IDCT module using dual-port RAMs and 4 shared multipliers at ≥95% utilization.
- SystemVerilog
- FPGA
- ModelSim
- SRAM
3D Spatial Measurement System
Designed a firmware driver in C within the Keil IDE to interface with a LiDAR sensor via I2C and UART. Implemented servo motor control logic for 360-degree scanning.
- C
- Keil
- UART/I2C
- MATLAB
Relevant Skills
Languages
- Python
- C/C++
- SystemVerilog
- Verilog/VHDL
- MATLAB
- Tcl
Technologies
- Xilinx Vivado
- Synopsys Design Compiler
- Speedgoat/dSpace
- Altium Designer
- Linux
- Git/Subversion
Protocols
- AXI4/AXI-Stream
- CAN/PCIe
- JTAG/I2C/SPI
- TCP/UDP
Explore
Get In Touch
I'm always open to opportunities to work on FPGA designs. Whether you have a question or just want to say hi, my inbox is always open!
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